Fault Simulation Model for i{sub}(DDT) Testing: An Investigation

摘要

In today's technologies, resistive shorting and open defects are becoming more predominant. Conventional fault models, and tools based on these models are becoming inadequate in addressing these defects resulting from new failure mechanisms. In prior works i{sub}(DDT) testing techniques have been shown to detect resistive defects. However, in order to incorporate i{sub}(DDT) based methods into production test flows, it is necessary to develop a fault simulation strategy to enable ATPG and fault coverage to be determined. To our knowledge, no practical technique exists to perform fault simulation for i{sub}(DDT) based methods. At the heart of the difficulty of developing a fault simulation strategy is the analog nature of the test observable. In this paper we investigate a fault simulation model that partitions the task of simulating the CUT (chip under test) into linear and non-linear components. We also propose a path isolation strategy for core-logic as a means of reducing the computational complexity involved in deriving I{sub}(DDT) signals in the non-linear portion. More specifically an Impulse Response based method is derived to eliminate the need for transient simulations of the entire CUT.