The floating well operation of bulk MOSFETs is studied at 77 K in order to get a better insight in the underlying physics. It will be shown that a metastable threshold voltage (VT) behaviour can be induced by sweeping the linear characteristics from accumulation to inversion gate bias. Depending on the magnitude of the drain bias, a positive or negative Vi shift is obtained. This is related to the injected substrate current in accumulation, which corresponds to a gate tunnelling current for low Vns and the Gate Induced Drain Leakage (GIDL) current at high VK. Evidence will also be presented that in the latter case, the occurrence of impact ionisation near the drain leads to the turn on of the parasitic bipolar transistor, causing abrupt changes (latch) in the drain current and transconductance.
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