FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit

摘要

This work explores the feasibility of implementing a floating point exponentiation unit on reconfigurable computing systems. A table-driven exponentiation unit was implemented using synthesizable VHDL. The project included creating pipelined submodules for implementing basic IEEE-754 single precision operations such as addition, multiplication, and division by 32. These modules were then linked together to form the overall unit. The designs were synthesized, placed and routed. s indicate that today's FPGAs are well suited for this operation.