Multiple scan chain has been used in DFT (design for test) architectures primarily to reduce test application time. Since power is an emerging problem, in this paper, we present a design technique for multiple scan chain in BIST (Built-in Self Test) to reduce average power dissipation and test application time, while maintaining the fault coverage. First, we partition the scan chain into a set of smaller chains of similar lengths in such a way, that the total number of scan transitions in the scan chain is minimized. Then, we use a novel scan re-ordering algorithm in each smaller chain to further reduce the transitions. Experiments on ISCAS'89 benchmarks show up to 46.2% (average 24.4%) power reduction using the proposed technique, compared to the scan partitions given in the RTL description. Unlike previous approaches, our solution is computationally efficient and test-set independent and thus, can be effectively applied to large BIST circuitry.
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