Volumetric signal processing hardware acceleration for mine detection

摘要

Digital signal processing algorithms for the detection of landmines using ground penetrating radar are computationally intensive if not due to algorithmic complexity, then due to the vast quantity of data which must be processed in real-time. As a result of this, surface area coverage rates using general purpose computers are limited without an additional investment in multiple central processing units and the parallelization of the executable. This results in an excess of unused resources with the associated cost both in terms of monetary cost and power consumption. The increase in power consumption alone also causes an increase cost in cooling and the requirement for larger prime power and/or reduced battery life. Field programmable gate array (FPGA) hardware devices are reconfigurable in seconds and they can be reprogrammed in the field using relatively standard equipment such as a laptop computer. A secondary advantage of re-configurable dedicated hardware is the flexibility it affords in terms of the specific signal processing algorithm being executed on the re-configurable computing device. As an example of this type of hardware optimization of an algorithm, this paper describes an implementation of volumetric (3D) template matching using re-configurable digital hardware, namely an FPGA. This is a viable alternative for the acceleration of digital signal processing and directly results in an increase in mine detection area coverage rates for a relatively small investment. This also results in a more compact, fieldable real-time implementations of landmine detection algorithms and a common mine detector whose hardware is standard but whose optimized algorithms are downloaded into the FPGA for the particular minefield to be cleared. In this paper we give a quantitative analysis of the increase in execution speed achieved by performing cross correlation of large template sizes on large data.