Carrier Transit Time Optimization of a High Speed Bipolar Transistor Using Numerical Device Simulation

摘要

The doping profile of a high speed silicon NPN bipolar junction transistor (BJT) was optimized using numerical device simulation (TCAD). A technique was employed in which the transient charge storage in the device was related to its carrier transit time, thereby providing a graphic demonstration of the impact of high carrier injection effects on the speed performance of the device. This knowledge enabled the engineering of a selectively implanted collector (SIC), which dramatically improved the switching frequency of the transistor over an identical device with a low-doped epi collector. The debiasing effect of the intrinsic collector resistance was also investigated for both devices. A comparison to preliminary measured electrical data is made for the transistor with the SIC.