VRM: Verilog RTL Model for High-Level Testing

摘要

The VLSI testing is being pushed to the high-level based technique. The paper proposes a Verilog Register transfer level Model (VRM) for integrated circuits. The model provides a text format file, which is convenient and more practical for developing succeeding Register Transfer Level (RTL) test tools, such as fault simulation, test pattern generation, testability measure and so forth. As an application, a RTL logic simulator with cycle-accurate was implemented.