首页> 外文会议>International Symposium on Microelectronics >Reliability Study of MCM-L with High I/Os Flip Chip and Laminated Board with Stacked vias in Build-up Layers
【24h】

Reliability Study of MCM-L with High I/Os Flip Chip and Laminated Board with Stacked vias in Build-up Layers

机译:具有高I / OS倒装芯片的MCM-L的可靠性研究和堆叠层堆叠通孔的层压板

获取原文
获取外文期刊封面目录资料

摘要

The reliability of MCM-L with high I/Os flip chip and build-up laminate with stacked vias was investigated in this paper. Accelerated thermal cycling(ATC) tests and failure analysis for six specimens with different structures and materials were conducted firstly to determine the fatigue life and failure mechanisms of the package. The results revealed that the CTE of board and underfill observably affected the fatigue life of the solder joints even when encapsulated with underfill, while the size of chip had little effect. For the specimens with single layer PI substrate, cracks all existed in upper solder joint near the chip, while for the specimens with build-up laminate, there existed two phenomena: for the specimens with lower CTE underfill, cracks mainly existed in upper solder joint near the chip, and the drum profile of the solder joints were destroyed to a certain extend, for specimens with higher CTE underfill, cracks not only existed in upper solder joint but also existed in the interface between solder joint and copper pad on the substrate, and the drum profile of the solder joints were kept well. Another phenomenon was that although there existed inner voids or air bubbles within the underfill after curing, no further delamination was found to propagate near these defects with the increased thermal cycles. Global-local FEA were then conducted to analyze the mechanical behavior of the package. The simulation results revealed that for the specimens with stacked vias, higher CTE underfill and board, solder joints underwent higher von Mises stress and strain, and then led to lower fatigue life, which showed that the simulation results could accounted for ATC tests results well. A fatigue life model in related with accumulated strain energy density of solder joint was built to estimate the solder joint fatigue life of the package, and the empirical constants were determined by fitting simulation and ATC tests results.
机译:本文研究了具有高I / OS倒装芯片的MCM-L的可靠性,并在本文中研究了具有堆叠通孔的堆积层压板。加速热循环(ATC)测试和失效分析具有不同结构和材料的六个样本,首先进行了措施,以确定包装的疲劳寿命和失效机制。结果表明,即使用底部填充填充,底板的CTE和底部填充的底部可观察地影响焊点的疲劳寿命,而芯片的尺寸效果几乎没有。对于具有单层PI衬底的样品,芯片附近的上焊点中的裂缝,而对于具有堆积层压板的样品,存在两种现象:对于具有较低CTE底部填充的样品,主要存在于上焊点中的裂缝在芯片附近,并且焊点的滚筒轮廓被破坏到一定延伸,对于具有较高CTE底部填充物的标本,不仅存在于上焊点的裂缝,而且在基板上的焊接接头和铜焊盘之间存在于界面中。并且焊点的滚筒轮廓保持良好。另一种现象是,尽管固化后底部填充物中存在内部空隙或气泡,但没有发现进一步的分层在这些缺陷附近与增加的热循环繁殖。然后进行全球局部FEA以分析包装的力学行为。仿真结果表明,对于具有堆叠通孔,更高的CTE底部填充物和板的标本,焊点接受了更高的von误判和应变,然后导致疲劳寿命较低,这表明仿真结果可能会占ATC测试结果。建立了疲劳寿命模型与焊接接头的累积应变能密度相关,以估计包装的焊点疲劳寿命,并且通过拟合模拟和ATC测试结果来确定经验常数。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号