Design and realization of a two input fuzzy chip running at a rate of 80 ns

摘要

A VLSI fuzzy chip with two 7 bit inputs has been designed to run at a rate of 80 ns. The chip has been designed in 0.7 /spl mu/m CMOS technology and to reach such a speed the architecture is pipelined and only the active rules are processed. The design uses the VHDL as a front-end tool and has been synthesized by the Cadence Opus SW obtained via Europractice using the cell-based digital 0.7 /spl mu/m CMOS ES2 technology library. The chip has been sent to the ES2 foundry to be constructed. The chip size is 14 square mm. The chip has been designed for high energy physics applications.