Bit-Matrix Decomposition and Dynamic Reconfiguration: A Unified Arithmetic Processor Architecture, Design and Test

摘要

This paper presents the architecture, design and test of a unified arithmetic processor, developed based on recently proposed partial product bit-matrix decomposition and dynamic reconfiguration parallel processing mechanism. By trading bitwidth for array size, the processor is able to perform several operations involving the multiplication of two 32-b numbers and two 4×4 matrices of 8-b numbers, as well as the evaluation of the inner product of two size-4 arrays of 16-b numbers. All of them are important to many applications including graphics and volume rendering. A set of very simple and efficient reconfigurable switches is utilized to achieve the high performance. Only two extra bits are needed for all reconfiguration controls. The architecture also possesses a superiority for high quality test. The circuit simulations with a 2.5V, 0.25μ process have shown that the processor performance including delay and VLSI area is comparable with the existing single-function counterparts.