Contamination Induced Risk Reduction through Improved Control Plan Implementation

摘要

Metallic contamination has long been known to be a key detrimental factor to device yield, causing degradation of electrical parameters like gate oxide breakdown voltage [1] and background noise in Charge Coupled Devices (CCD) [2] for instance. Thus, device manufacturing control plans systematically include monitoring of metal contamination at process steps which are potentially at risk and especially in the Front End of the Line (FEOL) area. This is commonly achieved in-line on monitor wafers through a combination of Total Reflectance X-Ray Fluorescence (TXRF) and post anneal Surface Photo Voltage (SPV). Unfortunately, with the ever increasing sensitivity of new technologies to trace metal contaminants and the wide range of metal behavior during thermal cycles, this type of control plan scheme often shows limitations both in terms of sensitivity/detection capabilities and risk coverage. In addition, control or specification limits are difficult to define since little is known concerning correlation of yield loss versus contaminant concentration. Finally, industrial requirements in terms of metrology capacity limitation and out-of-control process equipment downtime have to be considered when putting in place the most appropriate control plan as there will always be a trade off between risk assessment, cost and productivity. In this report we will show how, taking into account the aforementioned considerations we have improved our manufacturing control plan for metal contamination.