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Universal test complexity of field-programmable gate arrays

机译:现场可编程门阵列的通用测试复杂性

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A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading which makes FPGAs C-testable.
机译:现场可编程门阵列(FPGA)可以在字段中实现任意逻辑电路。在本文中,我们考虑了通用测试,使得当应用于未编程的FPGA时,它确保FPGA上的所有相应的编程逻辑电路都是无故障的。我们专注于测试FPGA中的查找表,并呈现两种类型的编程方案;顺序加载和随机接入加载。然后,我们将使用这些编程方案及其测试复杂性显示FPGA的测试程序。为了使FPGA的测试复杂性独立于FPGA的阵列大小,我们提出了一种称为块切片加载的编程方案,这使得FPGA C可测试。

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