Correlation between the Ageing and Grain Size of Polysilicon Thin-Film Transistors

摘要

A correlation between ageing under direct current and alternative current electric stresses and the grain size of low temperature polysilicon Thin Film Transistors is reported in this study. The active layer of these high performance transistors is amorphously deposited and then crystallized using a very large area excimer laser. Drain and source regions are solid phase crystallized. The ageing of TFTs occurs from state creation in the disordered regions of the channel material (particularly at the grain boundaries regions) and/or the channel-oxide interface. It is also favored by the high surface roughness of the laser crystallized films. Using Atomic Force Microscopy observations, the surface roughness and the grain size of three types of films crystallized at 566 mJ/cm~2, 635 mj/cm~2 and at 660mJ/cm~2 are determined. The obtained results with the first two films (566 ml/cm~2 and 635mJ/cm~2) show that although the mean roughness is similar, the grain sizes are different. Then the electrical aging of the transistors made using these two films is only due to the importance of the disordered regions. Using both bias stresses, we deduce that 635 ml/cm~2 transistors are clearly more stable. Moreover, the third film (660 mJ/cm~2) shows two types of structures in the same 5X5 cm~2 square substrate, one type with small grains and low roughness and (he other with large grains and high roughness. Although the roughness is higher in the type 2 region, transistors fabricated in this region are more stable. The stability originated then more from the quality of the structure.