A holistic methodology to address leading edge FPGA manufacturing challenge

摘要

A yield ramp methodology for Field-Programmable Gate Array (FPGA) in advanced technologies has been presented. By optimizing design based defect inspection setups, we can use defect-to-bit overlay mapping method more effectively and more reliably in product failure debug [1]. This is complimentary to the manufacturing fab's test vehicles, electrical tests and physical failure analysis for faster wafer failure root cause analysis. With integrating the critical area analysis and defect criticality calculation, this proven methodology provides fab-less and fab-lit companies more tools in their efforts of design for yield, design for manufacturing and design for tests.