Domain-Optimized FPGAs Address SoC Challenge

摘要

System-on-a-chip (SoC) design is becoming more complex — and more expensive. Soaring ASIC costs — at $10M and up for 130 nm CMOS technology — along with increased risk associated with new process technologies, is opening the door for a new generation of FPGA architectures to push into the system-on-a-chip (SoC) design realm previously dominated by ASICs. New 90 nm FPGA architectures are enabling domain-optimized platforms that can meet tough design specifications at a reduced cost, and they have the flexibility designers need to deal with current and evolving SoC applications. By combining high-performance, high-density programmable logic with extensive embedded memory resources and flexible high-speed I/O into a single chip, these devices serve as a starting point, or platform, that engineers customize to create circuits that implement their products with unique logic functions.