Control of crystalline defects in trench isolated thick film SOI for high voltage smart power ICs

摘要

We have studied the impact and control of trench related crystalline defects on thick film SOI for high voltage smart power ICs as well as those related to the wafer growth method, and evaluated their effects on device and circuit performance. We found that the deep trench etch coupled with the stress generated by the TEOS trench liner and polysilicon refill is the main source for creating crystalline defects such as slip dislocations. We also found that the doping level of the buried layer implant is an important contributing factor, while the trench profile also plays a role in slip generation. Careful optimization of the buried layer doping level and trench oxide liner thickness, and strict control of the trench profile is necessary to minimize the crystalline defect level and to achieve the desired electrical parameters. The choice of CZ and FZ wafers has a major impact on the surface defect density. In addition, the buried layer acts as an internal gettering layer to improve the minority carrier surface lifetime.