Power optimization issues in dual voltage design

摘要

In this paper, we look at power optimization issues under dual supply voltage environment, with the goal of optimizing power consumption due to interconnection and gate capacitances. Logic level synthesis is used as a good starting point of rpower reduction, while subsequent placement stage modifies or verifies logic level design by providing more accurate estimate of power dissipation. We try to reduce power dissipation due to gate capacitance at logic level using two supply voltages. This however imposes a constraint on the placement stage as the final placement has to conform to the specific layout structure. We discuss how both levels interact with one another, and propose an effective algorithm to find the tradeoff between power reduction and placement legality. Experimental results show that, on an average, a final power reduction of nearly 16percent is obtained by our approach.