Advanced procedure to evaluate process performance at very low k_1 based on device parameters linked to lithography and process data Part II: Verification of cell layout based on integration of optical and electrical simulations

摘要

This is an extension of our previous work where we discussed basic assumptions of device oriented process verification, Here, we propose an integrated procedure to verify the design of active devices and interconnections. It entails extraction of device, contact, and interconnect electrical performance based on optical simulation of layout geometries, including proximity correction features, combined with critical dimension (CD) variation and misalignment. A critical analysis, proposed in this work, made it possible to focus the simulation on the selected process corner options. We integrated multilevel optical and device simulation to verify dense layouts for deep sub-wavelength design rules in a six-transistor advanced memory cell.