In this paper, the efficiency of a fully adiabatic logic circuit is compared with its combinational and pipelined static CMOS counterparts. The performance of each circuit is studied in terms of the maximum operating frequency, the minimum operating voltage, the circuit energy consumption, and the switching noise generated by the circuit. An 8-bit carry look-ahead adder is designed using a 0.6 /spl mu/m CMOS technology for all three logic styles. Based on the post-layout simulation results, the adiabatic adder exhibits energy savings of 76% to 87% and 87% to 90% compared to its combinational and pipelined static CMOS counterparts, respectively. It also exhibits a considerable reduction in switching noise compared to its static CMOS counterparts.
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机译:本文将完全绝热逻辑电路的效率与其组合和流水线静态CMOS对应物进行比较。根据最大工作频率,最小工作电压,电路能耗和电路产生的开关噪声来研究每个电路的性能。为所有三个逻辑样式使用0.6 / SPL MU / M CMOS技术设计了8位携带展示前瞻加法器。基于后布局模拟结果,与其组合和流水线静态CMOS对应相比,绝热加法器的节能76%至87%,87%至90%。与其静态CMOS对应物相比,它还具有相当大的开关噪声减少。
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