A Novel Approach to Compact J-V Modeling for Deep-Submicron MOSFET's Technology Development and Circuit Simulation

摘要

This paper presents a novel approach to formulating compact I-V models for deep-submicron MOS technology development. The developed model is a one-region closed-form equation that resembles the same form as the long-channel one, which covers full range of channel length and bias conditions. Model parameter extraction follows a one-iteration prioritized sequence with minimum measurement data, and can be correlated to process variables.