FULLY RELAXED Si_(0.7)Ge_(0.3) BUFFERS GROWN ON PATTERNED SILICON SUBSTRATES FOR HETERO-CMOS TRANSISTORS

摘要

Aggressive scaling has lead to the outstanding improvements in the speed and performance of CMOS devices. Today, as scaling of silicon becomes more difficult, het-ero-MOSFETs (HMOSFETs) have become of greater interest. Computer simulations suggest that devices incorporating Si and SiGe layers and grown on a strain relaxed Si_(0.7)Ge_(0.3) buffer offer noteworthy advantages in performance (1). However, especially the realization of tensile strained Si for the n-type transistor and for a complementary transistor setup as well is difficult, requiring the implementation of a SiGe strain relaxed buffer (SRB) on Si substrates as a "virtual substrate". Up to now, thick compositionally graded SiGe buffers show the best performance for electronic devices but suffer from economical drawbacks. Additionally, because its low compatibility with the standard CMOS process they are little suitable for integration application e.g. to CMOS. A very promising integration approach utilizes the realization of heterostructures in a limited area, so called differential epitaxy (2). For this reason, we have systematically studied the growth of SiGe SRB layers with a Ge content up to 30 % by differential molecular beam epitaxy (MBE) in oxide windows which define the active device areas of HMOSFETs (3). However, with the choosen thickness of 200 nm for the SiGe SRB in these earlier investigations only a degree of relaxation of 50 % was achieved. In this paper, we report about new results of fully relaxed SiGe buffers with a thickness of about 750 nm, that is in the order of the thickness of the field oxide in the standard CMOS technology. It should be stated, that these results were obtained without additional injection of point defects. For the comparison of the methods see (4).