The most important advantage of on-chip DRAMs is high bandwidth between a DRAM and a processor. Many circuit technologies are used to enlarge the bandwidth [1]. For example, sense amplifier data are extracted by a number of data-lines parallel tothe bit-lines in some DRAMs. Even if these circuits are used, random accesses substantially degrade the bandwidth because row-address access and cycle time (tRAC) are much larger than column-address access and burst cycle time in conventionally designedDRAMs. Small tRAC is not essential in conventional graphic applications because of periodicity and locality of their memory accesses. However, the large tRAC has prevented DRAMs from being widely used as on-chip secondary caches.
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