A 100MHz IF, 400 MSample/s CMOS direct-conversion bandpass ∑△ modulator

摘要

Wireless receivers that digitize at the intermediate frequency (IF) offer more flexibility and programmability than do conventional fully analog superheterodyne receivers. Bandpass ΣΔ modulators are a promising technique for digitizingnarrow-band IF signals; however, conventional CMOS modulators are inadequate with current technology when the IF frequency is in excess of 70MHz. Existing bandpass ΣΔ modulators are implemented either in discrete-time (DT), typically usingswitched-capacitor (SC) circuits, or in continuous-time (CT) using integrated active filter circuits.