A 500MHz pipelined burst SRAM with improved SER immunity

摘要

One of the components key to increased mobile computer performance is level-2 (L2) cache memory, which is usually a high-frequency synchronous SRAM and typically consumes >2W [1]. This SEAM has to be housed in low-thermal-resistance package suchas the plastic ball grid array (PBGA). Power dissipation must be reduced, since battery life is prolonged and a lower-cost TQFP package can be used. In addition, cosmic-ray-induced single soft errors are becoming a problem, since memory cell nodecapacitance is reduced with reduction of memory cell size [2]. At high altitude (air flight level of 30,000ft), cosmic-ray-induced SER is increased by 2 orders of magnitude. This type soft error is significant for mobile applications.