A low power ΣΔ analog-to-digital modulator with 50MHz sampling rate in a 0.25 μm SOI CMOS technology

摘要

A second-order double-sampled analog-to-digital∑△ modulator is implemented in a 0.25μm fully-depleted silicon-on-insulator (FDSOI) CMOS process. FDSOI has a better subthreshold swing and reduced short-channel effect than traditional bulkCMOS, and therefore the threshold voltage and hence the supply voltage can be lowered for low power application.