High-level hierarchical HDL synthesis of pipelined FPGA-based circuits using synchronous modules

摘要

In this paper we present an approach to high-level synthesis of digital circuits from synchronous moules. The synthesister implemented takes as its input a functional description of the circuit in the form of a netlist using pre-defined functional modules with desired parameters, and produces an AHDL description as an intermediate circuit representation. The functional modules can be designs entered and produced using different design entry tools and de-sign compliers. The synthesis allows hardware resorce sharing, variable data path wideths, variable bit resolutions, and various number representations (e.g. parallel, serial, stochastic) for different parts of a circuit. As a result of synthesis, pipelined circuit analysis ensures coherent dataflow through the circuit is produced. At the end, the overall control unit that controls data flow through the circuit is automatically generated. The synthesiser presents the first part of the implementation of tool for the optimisation of circuit design for FPGAs as a target technology.