High-Level Synthesis of Pipelined Circuits from Modular Quene-Based Specifications

摘要

This paper describes a novel approach to high- level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system the designer specifies the circuit as a set of inde- Pendent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modu- Lar, asynchronous specification into a tightly coupled, fully syn- Chronous implementation in synthesizable Verilog.