Polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted considerable attentions for their applications in the active matrix flat-panel display (AMFPD) (1) because of the feasibility of integrating peripheral driving circuits and internal pixel switching elements. However, the high defect density in the grain boundaries and intra-grain of poly-Si channels will greatly influence the electrical characteristics and reliability of poly-Si TFTs (2). It has been reported that poly-Si TFTs with multi-narrow channels can effectively reduce the defect density in the channels, resulted in lower threshold voltage (Vu,), higher field-effect mobility (|x), lower leakage current in OFF state, deeper subthreshold swing (SS), and superior reliability (3). On the other hand, for the system on panel (SOP) and memory devices applications with greatly integrated circuits, it is necessary to shrink the feature sizes of TFTs to achieve high performance and packing density. However, the traditional planar poly-Si TFTs with the short channel suffer from severe short channel effects (SCE), such as Vth fall-off, larger leakage current and SS, and serious drain-induced barrier lowering (DIBL), which will greatly limit their
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