Traps located at the gate-oxide/silicon interface play a major role in determining device characteristics such as current-voltage (I-V) and capacitance-voltage {C-V) characteristics in polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with large grains. With respect to the I-V characteristics, recent studies (1-4) have revealed that the gradual increase in the subthreshold current is attributed primarily to the interface traps. Moreover, a drain current model that includes the influence of the interface traps has been recently proposed and has successfully reproduced this subthreshold behavior (5). On the other hand, the frequency dispersion of the C-V characteristics is caused by the interface traps. However, there are no capacitance models that can accurately reproduce this dispersion.
展开▼
