Silicon-based IC technology development has kept an incredibly steady pace of progress in the past three decades guided by Moore's Law. As we have seen recently, the pace seems even accelerating rather than showing any sign of slowing. There are growing concerns, however, for such a trend from the viewpoint of technical feasibility and of economical validity. The former subject covers quite a broad spectrum of issues such as lithography, interconnect, transistors leading to more circuit- and system-oriented questions for functional partitioning. The latter starts from return on investment and cost affordability, which results in "who should do what by how much" debates. At this moment, and even in the near future, the process integration phase of IC technology development requires the largest amount of experimental data and resources, which are translated into the number of silicon wafers, run in a development cleanroom. The subject discussed here is how we possibly can technology development methodology in which we achieve the same level of data content with improved efficiency in R&D.
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