Die cracking is one of the crucial issues that influences the reliability of flip chip assemblies. As the demand for inputs/outputs escalates, the die size required to handle these demands has also increased. This, in turn, has resulted in higher stresses in the die. Die cracking depends on a combination of several factors. These include back side defects induced in silicon during wafer fabrication, defects induced on the sides of the silicon die during the dicing process and properties of the encapsulant. In addition, die cracking may also occur due to inequalities in the forces that are applied on the package, for example, as a consequence of thermal loads. This paper discusses the different modes of die cracking seen in high end flip chip applications. The 'backside' defects introduced during wafer fabrication act as sites for stress concentration, thereby initiating vertical die cracking when the package is subjected to thermal loading. As the stresses required to cause vertical die cracking in flip chip applications are high, horizontal die cracking is more commonly witnessed. The relationship between the critical tensile stress required to cause vertical die cracking and the maximum allowable size of the surface defects is quantitatively stated. Factors that can help reduce the incidence of die cracking are discussed. These include an improved dicing process, a reduction of 'back side' defects, a reduction in the mismatch of the coefficient of thermal expansion (CTE) between the various constituents of a flip chip assembly, and a decrease in the warpage of the package.
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