FPGA Resource Optimization Method for Hardware in the Loop Real-time Simulation of Power Converters

摘要

For the Hardware-In-The-Loop (HIL) real-time simulation of power converters, it is contradictory between the model precision and FPGA resources when the power converter model is implemented in FPGA. To optimize FPGA resources, the quantitative relation of the time step, word-length, and model precision have been studied. Based on the Signal-Noise Ratio (SNR) theory, this paper proposes a quantitative algorithm to choose optimal time step and word-length that meet the model precision to minimize the FPGA resources in HIL real-time simulation. Taking the three-phase inverter with LC filter as the example, the algorithm has been proven by the offline simulation results. The comparative analysis results show that the word-length for 21 bits, time step for 100ns are the optimal choice to minimize the FPGA resources. Finally, this method is verified by comparing the HIL real-time simulation results with the real experimental results.