A Multi-layered Pipeline Architecture for the Chinese Characters Recognition Chip

摘要

In the recognition of Chinese handwritten characters, it is a pattern matching process with large number of standard patterns. This is the bottleneck of the recognition speed. In this paper, a multi-layered pipeline architecture is devised to solve this bottleneck. The technology of multi-bank storage, parallel computing, etc. is also implemented to optimize the architecture. Therefore, a high recognition speed is achieved. The experimental system is implemented on a Xilinx XC4013E FPGA chip. It will be migrated to a custom VLSI chip in the future.