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The MINC chip: Multistage Interconnection Network with Cache control mechanism chip

机译:MINC芯片:具有高速缓存控制机制芯片的多级互连网络

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The Multistage Interconnection Network with Cache control mechanism (MINC) is a hardware mechanism to control the cache coherent in a switch-connected multiprocessors using a crossbar or Multistage Interconnection Network(MIN). In the MINC, the directory is located on the shared memory module and the Reduced Hierarchical Bit-map Directory schemes(RHBDs) are used to reduce the directory. In order to reduce unnecessary packets caused by compacting the bit map in the RHBD, a small cache called the pruning cache is introduced in the switching element.
机译:具有高速缓存控制机制(MINC)的多级互连网络是一种硬件机制,用于使用横杆或多级互连网络(MIN)来控制开关连接的多处理器中的高速缓存相干。在MINC中,目录位于共享内存模块上,并且使用缩小的分层比特 - 映射目录方案(RHBD)来缩小目录。为了减少通过压缩RHBD中的位图引起的不必要的数据包,在开关元件中引入称为修剪高速缓存的小型高速缓存。

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