首页> 外文会议>IEEE International Caracas Conference on Devices >Design of the analog components for a high sampling rate continuous time /spl Sigma//spl Delta/ modulator in 0.4 /spl mu/m HEMT technology
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Design of the analog components for a high sampling rate continuous time /spl Sigma//spl Delta/ modulator in 0.4 /spl mu/m HEMT technology

机译:在0.4 / SPL MU / M HEMT技术中设计高采样率连续时间/ SPL SIGMA // SPL DELTA /调制器的模拟组件的设计

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The design of the key components for a high sampling rate /spl Sigma//spl Delta/ modulator implemented on a 0.4 /spl mu/m InGaP-InGaAs HEMT technology is described. The circuit, a 2nd-order continuous-time /spl Sigma//spl Delta/ modulator, has a fully differential architecture including pairs of highly linear V-I converters, high-speed opamps, high-speed 1-bit DAC units, and a new polarity alternating feedback (PAF) comparator. Working at a sampling rate of 4.9 GHz and a signal bandwidth of 100 MHz, the fabricated modulator exhibits 43 dB signal-to-noise ratio (SNR), equivalent to 7.2 bits resolution. The circuit occupies an active area of 0.9 mm/sup 2/, and dissipates 400 mW from a 3.2 V power supply. Such performance corresponds to the highest sampling rate and lowest power consumption for an oversampled A/D converter in III-V technology known to us.
机译:描述了在0.4 / SPL MU / M Ingap-Ingaas HEMT技术上实现的高采样率/ SPL SIGMA // SPL Delta /调制器的关键部件的设计。电路,2nd阶连续时间/ SPL SIGMA // SPLΔ/调制器具有全差分架构,包括对高线性VI转换器的对,高速opamps,高速1位DAC单元以及新的极性交流反馈(PAF)比较器。以4.9 GHz的采样率和100MHz的信号带宽工作,制造的调制器表现出43 dB的信噪比(SNR),相当于7.2位分辨率。该电路占据0.9mm / sup 2 /的有源区,并从3.2V电源耗散400 mW。这种性能对应于我们已知的III-V技术的过采样A / D转换器的最高采样率和最低功耗。

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