With the increase in the complexity of VLSI circuit design and the corresponding increase in the number of logic gates on a chip, logic design errors can frequently occur. In this paper we present an efficient approach to Design Error Detection and Correction when a small number of modifications can rectify the design. Our method is based on test vector simulation and Boolean function manipulation techniques. The proposed approach guarantees to return a solution, if such a solution exists in our modification model, in a short computational time. Experimental results show the robustness of our approach.
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