GaAs VLSI implementation of a 2.5 Gb/s ATM label translator

摘要

Routing tables for communication networks can be designed using several approaches, including table look-up, content-addressable Memory (CAM), hashing, and tries. This paper presents a GaAs VLSI implementation of an efficient table lookup algorithm for 2.5 Gb/s ATM switching systems. This algorithm presents some very promising features such as the number of Virtual Channels which can reach 30000 possible connections. An extra header of three bytes is attached to the cell header which contains policing and priorities information for use inside the switch. Routing information is performed by using the Virtual Path Identifier (VPI) and the Virtual Channel Identifier (VCI) in the incoming cell to access the header translation table. The VLSI chip is fabricated using 0.6 /spl mu/m gate GaAs MESFETs, by VITESSE Semiconductor and it is housed in a 132 pin LDCC package. The Label Translator chip is expected to operate at 311 MHz with an associated power dissipation of 4 W.