The difficulty of cost-effectively identifying Known Good Die (KGD) is increased in circuits requiring multiple die packaged in Multi-Chip Modules (MCMs). Such circuits typically have high frequency I/O signals which are difficult to measure using inexpensive test equipment. The cost of full Built-In Self-Test (BIST) can be prohibitive, particularly when device integration levels are low. This paper presents a scheme for testing die for functionality and speed at minimal cost. The scheme also allows testing of MCM traces and testing of on-chip circuits both before and after packaging. The scheme was developed for use in Rensselaer Polytechnic Institute's F-RISC/G 1 ns processor project.
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机译：在需要在多芯片模块（MCMS）中的多个模具的电路中增加了成本有效地识别已知优质模具（KGD）的难度。这种电路通常具有高频I / O信号，这难以使用廉价的测试设备测量。完整内置自检（BIST）的成本可能是禁止的，特别是当设备集成级别低时。本文提出了一种用于测试模具的方案，以实现功能和速度最小的成本。该方案还允许在包装之前和之后测试MCM痕迹和对片上电路的测试。该计划是开发用于Rensselaer Polytechnic Institute的F-RISC / G 1 NS处理器项目的。
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