首页> 外文会议>International Conference on VLSI Design >Current Collapse Reduction Technique Using N-Doped Buffer Layer into the Bulk Region of a Gate Injection Transistor
【24h】

Current Collapse Reduction Technique Using N-Doped Buffer Layer into the Bulk Region of a Gate Injection Transistor

机译:电流塌陷技术使用N掺杂缓冲层进入栅极注入晶体管的堆积区域

获取原文

摘要

GaN based transistors are subjected to current collapse. In this work a unique solution to this issue is presented by using a buried n-type doped region in the bulk region below the 2DEG channel. The proposed structure is named as "Buried n-doped Gate Injection Transistor (BNGIT)". TCAD simulation of the structure shows that this added layer increases the electron density in the channel just above it. Hence the loss of electrons due to traps can be compensated which results in current collapse free operation.
机译:基于GaN的晶体管经受电流塌陷。在这项工作中,通过在2DEG通道下方的散装区域中使用掩埋的n型掺杂区域来呈现该问题的唯一解决方案。所提出的结构被命名为“掩埋的N掺杂栅极注入晶体管(BNGIT)”。 TCAD模拟结构表明,该添加层增加了刚刚上方的通道中的电子密度。因此,可以补偿由于陷阱引起的电子损失,这导致电流塌陷的操作。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号