Stability Analysis of SRAM Designed Using In0.53Ga0.47As nFinFET with Underlap Region

摘要

In this paper, the static noise margin (SNM) performance of 6T-static random access memory (SRAM) cell has been demonstrated by utilizing sub-14 nm In_0.53Ga_0.47As nFinFET devices with underlap fin length (L_un) for low-voltage operation. The quantum corrected drift-diffusion model along with density gradient approach is used to perform the simulation for In_0.53Ga_0.47As nFinFET with 14 nm channel length. We have assessed the impact on the SRAM stability with the help of SPICE simulations using the BSIM-CMG model. Simulations have been carried out with different L_un values such as 0, 3, 6, 9 nm to extract SRAM stability parameters. The device with L_un= 9 nm has reported the Static Voltage Noise Margin (SVNM) and Write Trip Voltage (WTV) of 6T-SRAM with 281 mV and 251 mV, respectively using an N-curve technique.