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ANALYSIS METHOD FOR EASY TESTABILITY AND ANALYSIS SYSTEM FOR EASY TESTABILITY AS WELL AS DESIGN METHOD FOR EASY TESTABILITY

机译:易用性的分析方法和易用性分析系统以及易用性的设计方法

摘要

PROBLEM TO BE SOLVED: To provide an analysis system for easy testability, which executes an analysis for the easy testability by implementing analysis for the controllability/observability in a stage for describing hardware not depending on an architecture.;SOLUTION: In the analysis system for easy testability a function description data for defining a hardware function is input by using a format, which does not depend on the architecture, a register variable is recognized, which can be inferred by a store element in the function description data, an event, which will occur by adding random numbers to the register variables being recognized is simulated; and thus a cause for a reduced detection of defective rates by using LogicBIST is analysed based on a toggle rate/an event occurring rate of a bus and a net, and also variables in the function description data, through results of simulation.;COPYRIGHT: (C)2008,JPO&INPIT
机译:解决的问题:提供一种易于测试的分析系统,该系统通过在描述硬件而不依赖于体系结构的阶段中实现可控性/可观察性的分析,从而对易测试性进行分析;解决方案:易于测试,通过不依赖于体系结构的格式输入用于定义硬件功能的功能描述数据,可以识别寄存器变量,可以通过功能描述数据中的存储元素,事件来推断该变量通过将随机数添加到被模拟的寄存器变量中,将发生这种情况;因此,通过仿真结果,基于总线和网络的触发率/事件发生率以及功能描述数据中的变量,分析了使用LogicBIST减少缺陷率检测的原因。 (C)2008,日本特许厅&INPIT

著录项

  • 公开/公告号JP2008047150A

    专利类型

  • 公开/公告日2008-02-28

    原文格式PDF

  • 申请/专利权人 RICOH CO LTD;

    申请/专利号JP20070263384

  • 发明设计人 YAMADA TAKAMITSU;

    申请日2007-10-09

  • 分类号G06F17/50;G01R31/28;

  • 国家 JP

  • 入库时间 2022-08-21 20:21:12

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