Testability analysis system and method, and design for testability system and method

摘要

A testability analysis system analyzes testability by evaluating controllability and observability at the level of a hardware functional description independent of architecture. The testability analysis system comprises: an input part inputting functional description data to define a hardware function; a register variable identifying part identifying register variables whereby memory elements such as a flip-flop in said functional description data are inferred; a random pattern generator applying random patterns to the register variable identified by said register variable identifying part; a simulator conducting a simulation on an event caused by applying the random patterns; and an analysis part analyzing a cause of decrease of a fault coverage by LogicBIST, which is mainly caused by the difficulty of detecting faults by the random pattern test that PRPG (Pseudo Random Pattern Generator) of the Scan-Based LogicBIST executes, based upon toggle rates and simulation events of variables such as net and bus in said functional description data in accordance with a result of said simulation.