Delay Skew Reduction in IO Glitch Filter

摘要

Glitch filtering is an integral part of digital input signal conditioning. Filtering introduces delays in the system. Mismatches in rise and fall delay of the filter causes duty cycle distortion in the input resulting in system failure. A timing failure occurred in a product fabricated in CMOS 140nm TSMC process due to delay mismatch in IO glitch filter. A failure analysis is done and capacitor asymmetry at low voltage is found to be the root cause of delay mismatch. Drive transistor DC mismatch and output inverter threshold asymmetry were also contributing factors. The reasons of delay mismatch are analyzed and the steps taken to solve them are described in this paper.