Variable instruction issue for efficient MIMD interpretation on SIMD machines

摘要

Programming SIMD hardware to interpret (in parallel) programs and data resident in each PE is a technique for obtaining a cost effective, massively parallel MIMD processing environment. Although heavily dependent on each application that is interpreted, the performance of the synthesized MIMD environment is greatly influenced by the organization of the instruction interpreter. For example, it is possible to delay the interpretation of infrequent operations to improve the overall performance of the MIMD processing environment. Interpreters that attempt improved MIMD performance by deferring infrequent operations are called variable issue control loops. This paper examines the construction of optimized variable issue control loops. In particular, we study the problem of building control loops that optimize either (i) instruction throughput or (ii) PE utilization and present three heuristic algorithms for deriving near optimal variable issue control loops.