A FPGA ASIC communication channel systems emulator

摘要

The authors describe the FPGA implementation of a Communication Channel Systems (CCS) emulator designed for conducting hardware experiments in convolutional forward error correction. This flexible, new test platform provides verification and benchmarking for a wide range of ASIC convolutional decoder designs as well as decoding coprocessors. The system generates test patterns, inserts noise, enables extensive control of signal quantization, and can convolutionally encode with 4 bit soft decisions in any code type from rate 1/2 to 1/6 and any constraint length from 3 through 15.