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A pragmatic test pattern generation system for scan-designed circuits with logic value constraints

机译:具有逻辑值约束的扫描设计电路的语用测试模式生成系统

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In testing for practical logic circuits, there may exist logic value constraints on some part of logic circuits owing to various requirements on design and test. The inefficiency in handling the logic value constraints during the line justification stage of test generation may result in low fault coverage as well as excessive computer time with numerous fruitless searches. This paper presents a logic value system called taboo logic value to represent the logic value constraints and to identify additional logic value constraints using a taboo logic calculus. Also, a test pattern generation algorithm is discussed to show how the taboo logic system can be incorporated into existing test generation algorithms. Finally, experimental results demonstrate the efficiency of the taboo logic values.
机译:在测试实用逻辑电路时,由于设计和测试的各种要求,可能存在对某些逻辑电路的逻辑值约束。处理在测试生成的逻辑阶段期间处理逻辑值约束的效率可能导致低故障覆盖以及具有许多无果蝇的计算机时间。本文介绍了一个名为Taboo逻辑值的逻辑值系统,以表示使用禁忌逻辑微积分来识别其他逻辑值约束。此外,讨论了测试模式生成算法以显示如何将禁忌逻辑系统结合到现有的测试生成算法中。最后,实验结果表明了禁忌逻辑值的效率。

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