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Low Temperature Technology Options For Integrated High Density Capacitors

机译:用于集成高密度电容器的低温技术选择

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In recent years, integrated high-density capacitors have gained a lot of interest for RF and Mixed Signal IC applications. In this paper, we discuss technological options for integrated capacitors with capacitance densities up to 30fF/μm{sup}2. The capacitive structures where realized with dielectric materials such as Bi-Ta-O, Sr-Ta-O or Ta{sub}2O{sub}5. The Bi-Ta-O and Sr-Ta-O were deposited by means of Metal Organic Chemical Vapor Deposition (MOCVD) at 360°C. Films with densities up to 30fF/μm{sup}2 were obtained, the leakage current of the structures remained below 3·10{sup}(-8) A/cm{sup}2 at 3V for densities below 10 fF/μm{sup}2. In parallel, a dual dielectric layer process, with maximum fabrication temperature of 250°C, based on the anodic growth of Ta{sub}2O{sub}5 was yielding devices with leakage current below 1·10{sup}(-9) A/cm{sup}2 at 3V for 9.5 fF/μm{sup}2 capacitance density.
机译:近年来,集成的高密度电容器对RF和混合信号IC应用获得了很多兴趣。在本文中,我们讨论了具有电容密度的集成电容器的技术选择,高达30ff /μm{sup} 2。用介电材料实现的电容结构,例如Bi-Ta-O,SR-Ta-O或Ta {Sub} 2O {Sub} 5。通过360℃的金属有机化学气相沉积(MOCVD)沉积Bi-TA-O和SR-Ta-O.获得了高达30ff /μm{sup} 2的密度的薄膜,结构的漏电流在3·10 {sup}( - 8)a / cm {sup} 2,对于低于10 ff /μm的密度{ sup} 2。并行地,基于TA {Sub} 2O} 5的阳极生长,具有250℃的最大制造温度的双介电层工艺均产生漏电流低于1·10 {sup}( - 9)的装置A / cm {sup} 2在3v以9.5 ff /μm{sup} 2电容密度。

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