Modeling, Simulation and Implementation of a Passive Mixer in 130nm CMOS Technology and Scaling Issues for Future Technologies

摘要

In this paper, modeling, simulation, and implementation of double-balanced passive mixer are shown and examined. We analyze the performance of the mixer in terms of conversion gain (G{sub}C), 1-dB compression point, and Noise Figure (NF). We will show the accuracy of our model and analyses when compared with simulation and measured results for a 130nm technology based mixer design. We introduce a mixer's figure-of-merit (FOM{sub}(MIXER)) and briefly show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance.