A GaAs MESFET 7 Gb/s dynamic decision circuit IC

摘要

A GaAs MESFET dynamic decision circuit is reported that was operated at up to 7 Gb/s. A block diagram of the flip-flop is shown along with a detailed schematic diagram. The circuit consists basically of two differential amplifiers and two sample-and-hold gates operating in a manner similar to a master-slave D flip-flop. The circuit uses 0.5- mu m-gate GaAs MESFET technology and charge-cancelling techniques to obtain the 7-Gb/s clocking rate. A 0.6-V peak-to-peak output data eye is symmetrical and has 70 ps rise and fall times while retiming a noisy data input. The circuit operates from a single -6 V supply and dissipates 0.24 W of power. The chip's size is 0.5 mm/sup 2/.