Implementation of the Digital Logic for Reading-Out a 16X16 Pixel X-Ray Detector Array

摘要

In this paper we propose the digital logic required for reading-out a 16X16 array of X-ray detectors. The proposed read-out strategy allows us to handle an event rate as large as 106 event/s over the whole array and 104 event/s over a single row of the array. The digital logic is embedded in an integrated circuit to be bump-bonded on top of the detector, which includes also the front-end electronics required for processing the sensor output signals and the A/D converter. This work was carried-out in the framework of an ESA research activity.